(1) Field of the Invention
The present invention relates to the fabrication of dynamic random access memory (DRAM) devices, and more particularly to a method for fabricating improved bottom electrodes (capacitor nodes) using high-temperature film (HTF) polysilicon for increased capacitance and improved cycle refresh times and product yield.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) devices are used for storing digital information. The DRAM consists of an array of memory cells which are accessed by peripheral circuits on the chip for randomly reading and writing information to and from the individual memory cells. The most common memory cell consists of a single-current pass transistor, typically a field effect transistor (FET), and a single storage capacitor. With increased circuit density and reduced cell size, the capacitor area decreases, and it is important in the DRAM technology to maintain or increase the capacitor area while reducing the leakage current to provide sufficient signal-to-noise margins and to increase the refresh cycle times.
Recently, stacked storage capacitors have drawn considerable attention because they can be built vertically upward over the FETs in a variety of ways to substantially increase the surface area of the capacitors. However, these stacked capacitors require additional processing steps and are more costly to manufacture, compared to the more conventional process that uses a flat stacked capacitor structure.
One method of increasing capacitance on stacked capacitors is to use an interelectrode dielectric layer having a high dielectric constant between the capacitor electrodes. For example, Kamiyama in U.S. Pat. No. 5,438,012 teaches a method of forming a doped tungsten oxide as the interelectrode dielectric layer to increase capacitance and reduce leakage currents by reducing the dangling bonds in the dielectric. Kamiyama dopes the tungsten oxide with titanium and also suggests other dopants, such as silicon, boron, phosphorus, or germanium.
Sandhu in U. S. Pat. No. 5,438,019 teaches a method for forming a high quality silicon thin film using chemical vapor deposition (CVD) to replace the more expensive and slower process of using molecular beam epitaxy (MBE). Sandhu controls the source gas at the substrate to provide a continuous uniform layer of silicon to simulate the MBE process. However, Sandhu does not address the use of this CVD as a bottom electrode material for DRAM capacitors.
However, there is still a strong need to provide a bottom electrode structure having low node leakage current, and to provide higher capacitance independent of the vertical structure that is built.